1. Field of the Invention
The present invention relates generally to integrated circuit assembly, and more specifically to a method and apparatus for packaging a semiconductor device in order to achieve optimal high frequency performance of the device.
2. Description of the Prior Art
Integrated circuit assembly includes semiconductor packaging wherein a semiconductor device, referred to as a die or chip, is placed in a sealed environment to protect the device from exposure to outside elements. In accordance with typical semiconductor packaging methods, a die is attached to a paddle, or die flag, of a metal lead frame, and encapsulated in a plastic package. Typical packaging methods include forming an assembly by mounting a die to a lead frame using an epoxy, connecting bond pads of the die to the lead frame using gold or aluminum wires, and sealing the entire assembly using lids or thermoplastic setting compounds.
FIG. 1A shows a top plan view of a conventional semiconductor package at 10, the package 10 including a package body 12 having a lead frame (not shown), the lead frame having a paddle area indicated by a dashed line 14. The package body 12 is encapsulated in plastic, and of leads 16 of the lead frame extend outward from opposite sides of the package. FIG. 1B shows a side elevation view at 20 of the semiconductor package 10. Each of the leads 16 includes a lead foot 22 which provides for mounting the semiconductor package onto a board (not shown). As shown in FIG. 1B, the leads 16 may extend downward to a point even with a bottom surface 24 of the package. FIG. 1C shows an alternative configuration of a typical semiconductor package at 30 wherein a plurality of leads 32 of a lead frame extend downward beyond the bottom surface 24 of the package.
Semiconductor devices are usually packaged in accordance with a packaging technique that is suited to achieve specific performance requirements of the particular device. Many types of semiconductor devices have specific requirements for electrical grounding, heat dissipation, and power dissipation. For high frequency semiconductor devices, electrical grounding is an important design consideration because of the effect of electrical impedance, and particularly inductive impedance, on high frequency performance.
In one type of semiconductor device package, a bottom portion of the paddle of the lead frame is exposed, and forms a lower surface of the semiconductor package. The exposed portion of the paddle structure provides for enhanced heat dissipation. When affixed to a contact area of a circuit board, the exposed portion of the paddle provides electrical grounding for the semiconductor package. Selected bond pads of the die may be connected to the grounded paddle via ground wires. In a conventional semiconductor package, the ground wires traverse relatively large distances.
FIG. 2A shows a cross sectional side view of a conventional semiconductor package device at 36, the device including a die 38 attached to a flat paddle 40 formed by a planar member of a lead frame. The lead frame and die are encapsulated in plastic 44. A bottom portion 45 of the paddle 40 is exposed, and forms a lower surface of the semiconductor package 36. The exposed portion 45 of the paddle provides for enhanced heat dissipation. When affixed to a contact area of a circuit board, the exposed portion 45 of the paddle 40 provides electrical grounding of the paddle. Selected bond pads (not shown) of the die 38 are attached to the paddle 40 by ground wires 42. Because of the planar shape of the paddle 40, the ground wires 42 must extend a relatively long distance to connect the bond pads at the top surface of the die 38 to the surface of the paddle 40. The impedance of the relatively long ground wires 42 causes inductance effects at high frequencies which may result in excessive ringing and noise in the performance of the device. What is needed is a method and apparatus for packaging high frequency semiconductor devices wherein the lengths of grounding wires are minimized in order to minimize excessive inductance effects which could compromise the performance of the device.
Thermal dissipation is another important design consideration in packaging techniques for many different types of devices. Therefore, what is also needed is a method and apparatus for packaging high frequency semiconductor devices wherein thermal dissipation is optimized.
It is an object of the present invention to provide a method and apparatus for packaging high frequency semiconductor devices wherein the lengths of grounding wires are minimized in order to minimize excessive inductance effects which could compromise the performance of the device.
It is also an object of the present invention to provide a method and apparatus for packaging high frequency semiconductor devices wherein thermal dissipation is optimized.
Briefly, a presently preferred embodiment of the present invention provides an improved lead frame structure for use in a semiconductor package. The lead frame structure includes: a plurality of leads; a paddle structure electrically isolated from the leads, the paddle structure including at least one lower paddle section having a first top surface to which a die may be attached, at least one mesa section disposed proximate the paddle section and having a second top surface disposed at a different elevation than the first top surface, the lower paddle section and the mesa section being joined by a wall section; and a plurality of tie bars attached to the paddle structure for supporting the paddle structure; whereby contact pads of a die attached to the first top surface may be electrically connected to the second top surface and to the leads prior to encapsulation thereof. A plurality of tie bars extends from opposite edges of the paddle structure, the tie bars providing for stabilizing the paddle structure during package fabrication.
In one embodiment, the paddle section of the paddle structure is formed by a planar member having a substantially rectangular shape, wherein the mesa section surrounds the lower paddle section.
In another embodiment, the second top surface comprises a continuous surface that surrounds the first top surface. The paddle structure is formed by coining a generally rectangular lead frame portion having a plurality of relief holes disposed proximate corners thereof.
In a further embodiment, the paddle structure comprises a plurality of mesa sections disposed at opposite sides of the lower paddle section. At least one of the leads may include: a lead stitch post disposed at a distal end of the lead and providing a surface for wire bonding; an upper lead section disposed at a different elevation than the lead stitch post; and a medial riser section joining the lead stitch post and the upper lead section.
An important advantage of the semiconductor device package of the present invention is that the mesa section of the paddle structure enables the use of shorter grounding wires which allow for reduced inductive impedance. This reduction in inductive impedance enables enhanced high frequency performance of the device by minimizing excessive inductance effects which would compromise the performance of the device.
The foregoing and other objects, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiment which makes reference to the several figures of the drawing.